Referring now to FIG. 1, in a dynamic random access memory array having a folded bitline architecture, a plurality of rowlines, RL1-RL4, intersect a plurality of bitline pairs, BL1-BL2 and BL3-BL4. The intersection of each rowline and each bitline provides a memory cell location, and represents a uniquely addressable data bit. During a read operation, when the charge stored in a cell, MC1-MC8, is dumped to a one bitline of a bitline pair by activating the rowline associated with that cell, the other bitline of the bitline pair provides a reference voltage level. Each bitline pair has associated therewith both a P-channel sense amplifier that is responsible for pulling the bitline having the marginally higher voltage level up to a voltage level close to power supply voltage, and an N-channel sense amplifier that is responsible for pulling the bitline having the marginally lower voltage level down to a voltage level close to ground potential.
Since the maximum voltage than can be written to a DRAM cell (V.sub.M) is equal to the voltage applied to wordlines V.sub.WL minus a threshold voltage (V.sub.t), V.sub.M is the optimum voltage level to which bitlines should be pulled up by the P-channel sense amplifiers. In the interest of longer refresh periods, lower soft error rate, and more robust capability to distinguish between a stored "0", and a stored "1" it has been found useful to apply a voltage to the wordlines that is greater than the power supply voltage V.sub.CC so that full power supply voltage can be written to a cell to represent a "1" value. U.S. Pat. Nos. 4,543,500 and 4,533,843, both of which issued to Joseph C. McAlexander, III, et al. describe such a technique. In fact, the voltage applied to the wordlines is typically considerably greater than a V.sub.t amount above V.sub.CC, as this permits much faster voltage transitions. This is due to the fact that current flow through the access transistor ramps down rapidly as the voltage on the bitline approaches a V.sub.t amount below the wordline voltage.
Referring once again to FIG. 1, the DRAM array depicted therein has non-bootstrapped wordlines (i.e., V.sub.WL is equal to the power supply voltage) and a prior art pull-up circuit for P-channel sense amplifiers. For such an array, V.sub.M is, of course, equal to V.sub.CC -V.sub.t. It will be noted that each digit line pair DL1-DL2 and DL3-DL4 in this DRAM array is shared by two memory sub-arrays, SA1 and SA2, with each digitline pair having a single P-channel sense amplifier, PS1 and PS2 located at one end of the digit line pair, and a single N-channel sense amplifier, NS1 and NS2, located between the two subarrays. Each P-channel sense amplifier (PS1 and PS2) is coupled to the pull-up node P.sub.VT through a P-channel write device (PW1 and PW2, respectively). Each P-channel write device is controlled by signal WT. Each N-channel sense amplifier (NS1 and NS2), on the other hand, is coupled to ground through an N-channel coupling transistor, NC1 and NC2, which are controlled by signal NLAT.
Still referring to FIG. 1, each sub-array is isolable from the N-channel sense amplifier by means of a natural N-channel isolation device in each digit line, ISO1-ISO8. Each digit line in a digit line pair is coupled to separate input/output lines, IO1 and IO2. The input/output lines IO1 and IO2 are coupled to multiplexers MUX1 and MUX2, respectively. By having two sub-arrays share a digit line pair, and by activating only one pair of isolation devices so that only the sub-array being addressed is coupled to the N-channel sense amplifier during sensing operations performed by the N-channel amplifier, digit line capacitance may be effectively halved. Once an N-channel sense amplifier has begun to pull one of its associated digit lines to ground potential, the remaining pair of isolation devices is activated in order to (in the case of the lower array) couple the digit lines to the P-channel sense amplifier, and (in the case of the upper array) couple the digit lines to the N-channel column decode transistors DQ1-DQ4. The column decode transistors are activated by a column decoder, CD, which is coupled to the address buss AB.